In contemporary operational amplifiers, isolation of the voltage of the input signals applied to the input ports from the load at the output port is a common goal, as is the goal of optimal gain. With reference to the example of Prior Art FIG. 1, first and second input signals are provided at input nodes inp, inm at the bases of first and second input transistors q1, q2 respectively. Current sources i2, i1 are coupled between a positive supply voltage VPLUS and the collectors of transistors q1, q2 respectively. The emitters of transistors q1, q2 are jointly coupled to a current source i5, in turn coupled to a negative supply voltage VMINUS. Collectively, the transistors q1, q2 and current sources i1, i2, and i5 comprise a transconductance stage 22 for the amplifier for converting voltage signals applied at the input nodes inp, inm to current signals at nodes N1, N2.
The output nodes N1, N2 of the transconductance stage are provided to the emitters of a folded cascode transistor pair 24, comprising first and second transistors q3, q4. The bases of the transistors q3, q4 are jointly coupled to a voltage source v1, in turn coupled to the positive supply voltage VPLUS, while the collectors are coupled to a current mirror 26. The current mirror 26 comprises transistors q6, q7, and q8, configured as shown, the emitters of which are coupled to resistors r6, r1 and r2 respectively. Collectively, the transconductance stage 22, the folded cascode pair 24, and current mirror 26 comprise an input stage 28, the output of which is provided at a high-impedance node N3. The resulting signal at the high-impedance node N3 represents the difference in current carried by transistors q1 and q2, which is, in turn, a function of the difference in voltage supplied by the first and second input signals at the input nodes inp, inm. The resulting signal at the high-impedance node N3 is provided to an output stage 30.
Output stage 30 includes a gain stage 32, a current source 34, and an output buffer 36. The gain stage 32 amplifies the signal provided at the high-impedance node N3. The current source 34 in combination with the current source i6 bias the transistors q10, q14 of the gain stage 32 to produce the voltage gain, resulting in an amplified difference signal at node N4. The output buffer 36 buffers the amplified difference signal at node N4 to produce a buffered output signal at the output node OUTPUT.
This configuration suffers from a number of limitations. For example, assuming the current provided by the current source 34 to be a constant current, and assuming a positive load current drawn by a load at the output node OUTPUT, the base current at transistor q17, for example comprising an NPN transistor, would be represented by the load current divided the beta, or gain, of transistor q17. Therefore, due to the positive load, the base current of transistor q17 is elevated, and, as a result, less current is provided to the collector of transistor q14. Consequently, it follows that less current is provided to the base of transistor q14, which results in less current drawn from the transistor q10 emitter, corresponding to less current being drawn from the base of transistor q10 at the high-impedance node N3.
Similarly, for a negative load current drawn at the OUTPUT node, transistor q16 becomes active, rather than transistor q17, and the base current at transistor q16, for example comprising an PNP transistor, is represented by the load current divided the beta of transistor q16. Due to the negative load, the base current of transistor q16 is elevated, and, following the explanation above, this corresponds to more current being drawn from the base of transistor q10 at the high-impedance node N3.
Any variance in the base current of q10 causes a corresponding change in the input voltages at the input nodes inp, inm that provide the q10 base current. This is an undesirable outcome, since an important function of the amplifier is the isolation of the input terminals from the load at the output terminals. This modulation of the current into the high-impedance node is referred to in the art and herein as an xe2x80x9cerror currentsxe2x80x9d.
Additionally, during the fabrication process, it is difficult to generate PNP and NPN transistors having the same beta on a common integrated circuit. Since the output stage 36 NPN transistor q17 and PNP transistor q16 are likely to have different betas, their base currents are affected differently by the same load. This translates to a different effect on the high-impedance node N3, and, in turn, a modulation of the voltages at the input nodes inp, inm to different degrees, depending on whether the load is drawing a positive or negative current.
Furthermore, nearly all transistors are subject to a phenomenon referred to as the xe2x80x9cEarly effectxe2x80x9d, which represents a difference in current at the collector of a transistor for a given base-emitter voltage, as a function of the collector-emitter voltage. In the Prior Art configuration of FIG. 1, the Early voltage effects for output stage transistors q14 and q15 will likewise cause a variance in the base current of transistor q10 at the high-impedance node N3, in turn causing a modulation of the input voltages at input nodes inp, inm, as described above. In the present case of FIG. 1, changes to the transistor q14 collector current can occur as a function of the transistor q15 Early voltage effect, as well as changes to the transistor q14 base current (beta) as a function of transistor q14 Early voltage. Any variance in the transistor q14 collector current and beta will result in modulation of the transistor q14 and transistor q10 base currents, which ultimately modulates the input voltage of nodes inp and inm at the input stage 28, as described above.
The present invention is directed to a differential amplifier that addresses the limitations of the prior art. In doing so, the present invention provides an amplifier having greatly enhanced open-loop gain, while maintaining performance-characteristics.
Particularly, the present invention is directed to a current compensation stage for an amplifier, for example an operational amplifier, that compensates for any modulation of current occurring at the high-impedance node. Furthermore, the configuration of the present invention reduces the error current at the high-impedance node resulting from a mismatch in beta between PNP and NPN transistors in the output stage, and reduces any error current resulting from the Early voltage effects of transistors in the current source and gain stage of the output stage. In this manner, the present invention serves to substantially isolate the amplifier input stage from the output load, and from any beta mismatch or Early voltage effects in the transistors of the output stage.
In a first embodiment, the present invention is directed to an amplifier comprising an input stage and an output stage coupled at a high-impedance node, and a compensation circuit. The input stage generates a difference signal that is a function of the difference in voltage between first and second input signals applied to first and second input ports. The difference signal is provided at the high-impedance node. The output stage is coupled to the high-impedance node of the input stage, and includes an output circuit coupled to the high-impedance node. The compensation circuit is also coupled to the high-impedance node such that any error current drawn from the high impedance node by the output circuit is substantially minimized by the compensation circuit.
The difference signal may comprise a current signal and the first and second input signals may comprise voltage signals. The output circuit may comprise a voltage gain stage as well as an output buffer.
The voltage gain stage may comprise: a first transistor, a base of which is coupled to the high-impedance node, an emitter of which is coupled to a current source, and a collector of which is coupled to the compensation circuit; and a second transistor, a base of which is coupled to the emitter of the first transistor, an emitter of which is coupled to a negative voltage source, and a collector of which is coupled to an output stage of the output circuit.
The output circuit may include a first transistor having a base, emitter and collector, the base being coupled to the high-impedance node, the emitter being coupled to a gain stage of the output circuit. The compensation circuit may include a sense transistor cascoded to the collector of the first transistor for generating, at the base of the sense transistor, a compensation current substantially equal in magnitude to the error current. A current mirror transistor, a collector of which is coupled to the base of the first transistor at the high-impedance node, provides the compensation current to the high-impedance node. A bootstrapping transistor, a base of which being coupled to the emitter of the first transistor, and an emitter of which is coupled to an emitter of the current mirror transistor, bootstraps the voltage at the collector of the first transistor to the base of the first transistor, and bootstraps the voltage at the collector of the sense transistor to the voltage at the base of the first transistor.
The compensation circuit may further optionally include: a second transistor, an emitter of which is coupled to the collector of the sense transistor, a collector of which is coupled to a positive voltage source, and a base of which is coupled to a current source; a resistor, coupled between the base of the second transistor and the emitter of the current mirror transistor; and first and second diodes coupled between the emitter of the current mirror transistor, and the emitter of the bootstrapping transistor.
The first transistor, the sense transistor, and the second transistor may comprise NPN transistors, while the current mirror transistor and the bootstrapping transistor may comprise PNP transistors.
A current mirror, for example a Wilson-style current mirror, may also be coupled to the high-impedance node.